diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a6f2e7a..403156b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1986,6 +1986,25 @@
 	  Support for durian platform.
 	  It has 2GB Sdram, uart and pcie.
 
+config TARGET_POMELO
+	bool "Support Phytium Pomelo Platform"
+	select ARM64
+	select DM
+	select AHCI
+	select SCSI_AHCI
+	select AHCI_PCI
+	select BLK
+	select PCI
+	select DM_PCI
+	select SCSI
+	select DM_SCSI
+	select DM_SERIAL
+	select DM_ETH if NET
+	imply CMD_PCI
+	help
+	   Support for pomelo platform.
+	   It has 8GB Sdram, uart and pcie.
+
 config TARGET_PRESIDIO_ASIC
 	bool "Support Cortina Presidio ASIC Platform"
 	select ARM64
@@ -2257,6 +2276,7 @@
 source "board/variscite/dart_6ul/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/phytium/durian/Kconfig"
+source "board/phytium/pomelo/Kconfig"
 source "board/xen/xenguest_arm64/Kconfig"
 source "board/keymile/Kconfig"
 
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e53ad53..56ed7b6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1188,6 +1188,7 @@
 dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
 
 dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
+dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
 
 dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
 
diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts
new file mode 100644
index 0000000..3f809c0
--- /dev/null
+++ b/arch/arm/dts/phytium-pomelo.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Phytium Pomelo board
+ * Copyright (C) 2021, Phytium Ltd.
+ * lixinde         <lixinde@phytium.com.cn>
+ * weichangzheng   <weichangzheng@phytium.com.cn>
+ */
+/dts-v1/;
+
+/ {
+	model = "Phytium Pomelo Board";
+	compatible = "phytium,d2000-pomelo", "phytium,d2000";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	sysclk_48mhz: clk48mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0x0>;
+		clock-frequency = <48000000>;
+		clock-output-names = "sysclk_48mhz";
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		uart0: serial@28001000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0x28001000 0x0 0x1000>;
+			clocks = <&sysclk_48mhz>;
+		};
+
+		pcie@40000000 {
+			compatible = "pci-host-ecam-generic";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0x0 0x40000000 0x0 0x10000000>;
+			ranges = <0x01000000 0x00 0x00000000 0x0  0x50000000 0x0  0x00F00000>,
+			 <0x02000000 0x00 0x58000000 0x0  0x58000000 0x0  0x28000000>,
+			 <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10  0x00000000>;
+		};
+	};
+};